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Abstract visualization for the publication: An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems

An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems

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An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems

Authors

Sepideh Asgari, Amirhossein Mohammadpanah, Ebrahim Ghafar-Zadeh, Sebastian Magierowski

Venue

IEEE Canadian Conference on Electrical and Computer Engineering

Conference Paper

2024

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    An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems | BioSA Lab | BioSA Lab